1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a non-volatile memory device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for increasing a coupling ratio of the device and simplifying the process for fabrication.
2. Discussion of the Related Art
FIG. 1 illustrates a schematic view of a conventional non-volatile memory device having a simple stack structure. The conventional non-volatile memory device includes a p-type semiconductor substrate 1, a tunneling oxide layer 2 on the substrate 1, and a floating gate 3 on the tunneling oxide layer 2. A control gate 5 is over the floating gate 3 and a dielectric layer 4 is between the floating gate 3 and the control gate 5. N-type impurity regions 6 are formed in the p-type semiconductor substrate 1 at both sides of the floating gate 3.
However, the conventional non-volatile memory device having the simple stack type has a disadvantage in a coupling constant of the control gate 5. As a cell size becomes small, the coupling constant also becomes small. To solve this problem, an ONO (Oxide/Nitride/Oxide) structure has been used as the dielectric layer 4 between the floating gate 3 and the control gate 5. Nonetheless, this is not a desirable solution for the problem because the process becomes complicated and annealing should be executed at a high temperature.
Moreover, at least one metal contact has to be formed for every two cells in constructing a cell array of the conventional non-volatile memory device as shown in FIG. 1. Thus, an effective cell size becomes larger. Accordingly, much effort for development and research has been directed to non-volatile memory devices to eliminate metal contacts in solving the problem.
FIG. 2 is a layout of the conventional non-volatile memory device not having a metal contact. FIG. 3 is a cross-sectional view showing a structure of the non-volatile memory device taken along line III--III of FIG. 2.
In the conventional non-volatile memory device not having a metal contact, additional metal lines for bit lines are not required. Instead, source and drain regions are used as the bit lines. In other words, a plurality of pairs of n-type heavily doped impurity regions 12 are formed in parallel in a semiconductor substrate 11 and separated from each other by a predetermined distance. Word lines (control gates) 13, separated from each another by a predetermined distance, are also formed on the semiconductor substrate 11 and perpendicular to the impurity regions 12. Floating gates 14 are formed on the word lines 13 and the impurity regions 12. A dielectric layer 16 (shown in only FIG. 3) is formed between the word lines 13 and the floating gates 14. A tunneling insulating layer 17, for example, oxide, is formed between the floating gates 14 and the semiconductor substrate 11. Source and drain regions of the impurity regions 12 used as bit lines are isolated from each other by an isolating layer 15.
In the conventional non-volatile memory device not having a metal contact, a bit line is not required for each cell, but only one metal contact for every 16 cells is needed because of resistance of impurity regions. Thus, the effective cell size is reduced.
Nevertheless, since the non-volatile memory device not having a metal contact has the simple stack structure, it still has the problem of low coupling. As an effort to solve the low coupling of the conventional non-volatile memory device shown in FIGS. 2 and 3, another conventional non-volatile memory having a different structure has been suggested.
FIG. 4 is a layout of another conventional non-volatile memory device to improve the low coupling of the conventional non-volatile memory device shown FIGS. 3 and 4. FIG. 5 is a cross-sectional view showing a structure of the non-volatile memory device, taken along line V--V of FIG. 4.
Heavily doped n-type impurity regions 22a, 22b, and 22c are formed in parallel in a semiconductor substrate 21. An oxide layer as a tunneling insulating layer 27 is formed on the entire surface of the semiconductor substrate 21. A plurality of first floating gates 24a and 24b having a matrix form are formed on portions of the tunneling insulating layer 27 between the impurity regions 22a, 22b, and 22c. An insulating layer 28 is formed on the tunneling insulating layer 27 between the first floating gates 24a and 24b. A plurality of second floating gates 24c are formed on the pairs of the first floating gates 24a and 24b. Word lines (control gates) 23 are formed on the semiconductor substrate 21 including the first and second floating gates 24a, 24b, and 24c and perpendicular to the impurity regions 22a, 22b, and 22c. The word line 23 also covers the first and second floating gates 24a, 24b, and 24c. A dielectric layer 26 (shown in only FIG. 5) is formed between the word line 23 and the second floating gate 24c. In this structure, the two adjacent first floating gates are connected with the second floating gate 14c, thereby increasing the coupling ratio.
Therefore, the impurity region 22b under the second floating gate 24c is used as a common drain region, and the impurity regions 22a and 22c at both sides of the second floating gate 24c are used as source regions. In addition, all impurity regions 22a, 22b, and 22c are used as bit lines.
However, the conventional non-volatile memory device for improving the low coupling ratio has the following problems yet to be solved. Although two first floating gates are connected with a second floating gate to increase the coupling ratio, each cell contacts the second floating gate with the first floating gates formed on two channel regions having an identical tunneling insulating layer, and thus increase in the coupling ratio is limited. Furthermore, since first floating gates are formed on the channel regions between the impurity regions, and the two adjacent first floating gates are connected with the second floating gate and a word line is formed thereon, the process to fabricate this type of device is still complicated so that reliability of the device is greatly reduced.